fJscaler Announces Sampling of Breakthrough 100 GHz BiCMOS TIA for Next-Generation AI and Cloud Datacenter Optical Interconnects

Company also unveils new Photonic IC product family targeting 1.6T coherent-lite and IM-DD applications

MÁLAGA, Spain, September 21, 2026--fJscaler, Inc., an innovator in high-performance analog and photonic semiconductors for optical interconnects, today announced at ECOC 2026 that it has begun sampling to strategic customers its BiCMOS transimpedance amplifier (TIA) for intensity-modulation direct-detection (IM-DD) applications. Designed for next-generation optical interconnects powering AI and cloud datacenters, the device delivers an unprecedented combination of energy efficiency, sensitivity, and speed.

As AI clusters scale to hundreds of thousands of accelerators, the power consumed by optical interconnects has become a first-order constraint on datacenter design. The new TIA achieves a power efficiency of 0.85 pJ/bit, an input-referred noise density of just 18 pA/√Hz, and a bandwidth of 100 GHz. These results redefine the performance envelope for direct-detect receiver front-ends. The device is also optimized for operation with a back-illuminated InP photodiode, and a next-generation version is in development targeting silicon photonics receivers. By pushing receiver energy below one picojoule per bit while extending bandwidth to 100 GHz, fJscaler's TIA enables 200G-per-lane and beyond serial links with the sensitivity headroom needed for low-power, unretimed, and linear-drive architectures.

"The economics of AI infrastructure are now written in picojoules per bit," said Jan Filip Chief Executive Officer of fJscaler. "Every fraction of a picojoule we remove from the optical link translates directly into more compute per watt and per dollar for our customers. With this TIA sampling to strategic customers today, we are giving module and system makers a receiver front-end that supports the 1.6T and 3.2T generations of optical interconnects without compromising on sensitivity or power. This is exactly the kind of leap the industry needs to keep scaling AI clusters sustainably."

"Reaching 100 GHz of bandwidth at 0.85 pJ/bit, with noise as low as 18 pA/√Hz, required rethinking the receiver front-end from the ground up," said Marco Vitali, Chief Technology Officer of fJscaler. "Our BiCMOS platform lets us combine the raw speed of SiGe with the integration density of CMOS, and pairing the TIA with a back-illuminated InP photodiode minimizes parasitics right at the optical-electrical interface. The result is a receiver that preserves signal integrity at 200G per lane and beyond, with the dynamic range and linearity that linear pluggable optics and co-packaged architectures demand. Our next generation extends the same architecture to silicon photonics receivers, opening the path to fully integrated, high-volume solutions."