SEEQC Demonstrates Quantum Error Correction Performance Gains with Industry First Digital Interface Optimized Decoder Architecture using NVIDIA Ising and NVQLink

Integration of SEEQC's chip-based pre-decoder architecture with NVIDIA Ising, leveraging the all-digital interface of SEEQC's Digital Link with NVIDIA NVQLink, delivers approximately 50% improvement in key decoding performance metrics

ELMSFORD, N.Y. & SANTA CLARA, Calif., October 22, 2026--SEEQC, Inc. ("SEEQC" or the "Company"), a chip-based quantum computing company, today announced results demonstrating significant performance improvements in quantum error correction decoding through a digital interface optimized multi-stage decoding architecture combining SEEQC's chip-based pre-decoder technology with the NVIDIA Ising open family of AI models.

SEEQC's chip-based pre-decoder was integrated in a simulated quantum processor and architecture stack incorporating realistic decoder latency at scale, as a backend to NVIDIA Ising Decoding with SEEQC Digital Link and NVIDIA NVQLink providing the framework for low-latency communication between quantum and GPU-accelerated compute environments. Compared with operating NVIDIA Ising as a standalone pre-decoder, the combined multi-stage pre-decoder architecture demonstrated an approximately 50% reduction in decoding latency and logical error rate performance, the two key metrics that dictate the scalability of a fault tolerant quantum system. The overheads associated with error correction are enormous and can increase exponentially as systems scale towards useful computation. Therefore, a 50% improvement in these key scaling bottleneck metrics have a significant impact on the overall scalability and efficiency of a quantum processor.

The results demonstrate how specialized processing integrated at a chip-scale closer to the QPU complements GPU-accelerated decoding to improve performance of the overall quantum-classical system. By reducing the amount of information transferred to higher-level classical compute resources and accelerating critical decoding functions, the architecture provides a potential path toward faster and more scalable quantum error correction, whilst lowering the overheads and performance requirements of the underlying quantum processor.

"We believe the future of quantum computing will be enabled by the tightest possible integration of quantum processors with advanced high-performance computing infrastructure," said John Levy, Chief Executive Officer of SEEQC. "These results demonstrate the role SEEQC's digital chip technology can play at that critical interface. Bringing specialized processing closer to the qubits while connecting efficiently to GPU-accelerated computing provides a pathway toward quantum systems that can operate at significantly greater scale."